The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 26, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seung Wan Shin, Suwon-si, KR;

Ho Jun Jung, Suwon-si, KR;

Seung Chul Oh, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/56 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.


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