The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2020
Filed:
Apr. 24, 2014
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Yu-Ting Huang, Hsinchu, TW;
Hsiang-Wei Lin, New Taipei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/485 (2013.01); H01L 21/743 (2013.01); H01L 21/76802 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76885 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract
The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.