The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Nov. 13, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Yean Ling Teo, Goyrans, FR;

Aaron A. Geisberger, Austin, TX (US);

Laurent Cornibert, Toulouse, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B61B 7/02 (2006.01); B81B 7/02 (2006.01); B81B 7/00 (2006.01); G01D 18/00 (2006.01); G01L 1/18 (2006.01); H01L 23/31 (2006.01); H01L 29/167 (2006.01); H01L 29/36 (2006.01); H01L 29/84 (2006.01);
U.S. Cl.
CPC ...
B81B 7/02 (2013.01); B81B 7/008 (2013.01); G01D 18/00 (2013.01); G01L 1/18 (2013.01); H01L 23/3114 (2013.01); H01L 29/167 (2013.01); H01L 29/36 (2013.01); H01L 29/84 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0264 (2013.01); B81B 2207/012 (2013.01);
Abstract

A microelectromechanical systems (MEMS) device and a method for calibrating a MEMS device. The device includes a first semiconductor substrate including at least one MEMS component. The device also includes an application specific integrated circuit (ASIC) comprising a second semiconductor substrate. The second semiconductor substrate is attached to the first semiconductor substrate. The second semiconductor substrate includes at least one piezoresistive strain gauge. Each piezoresistive strain gauge includes at least one doped semiconductor region having a resistivity that is determined by a strain on said doped semiconductor region. The second semiconductor substrate also includes a circuit for evaluating a trim algorithm for the at least one MEMs component using one or more output values received from the at least one piezoresistive strain gauge.


Find Patent Forward Citations

Loading…