The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Jun. 06, 2019
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Kevin B. Leigh, Houston, TX (US);

Everett Salinas, Houston, TX (US);

Richard Barnett, Houston, TX (US);

Michael Chan, Houston, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 7/14 (2006.01); H01L 23/498 (2006.01); G02B 6/42 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 7/1417 (2013.01); G02B 6/428 (2013.01); H01L 23/49816 (2013.01); H05K 1/0274 (2013.01); H05K 1/0298 (2013.01); H05K 1/113 (2013.01); H05K 1/144 (2013.01);
Abstract

A high-density universally-configurable system board architecture for use with multiple mid-board optic (MBO) type configurations is provided. The system board comprises a switch application specific integrated circuit (ASIC) assembly, a plurality of MBO interfaces comprising a plurality of via-in-pad plated over (VIPPO) vias, and a plurality of mounting holes. Each MBO interface is configured to mate with a soldered-down MBO assembly or a socket instance comprising a socketized MBO assembly. Each socketized MBO assembly comprises an interposer comprising a plurality of VIPPO vias, where the bottom contact pad of each VIPPO via is thicker than the top contact pad. Either configuration is facilitated without the need to modify the system board layout.


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