The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Mar. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mats Gustav Agerstam, Portland, OR (US);

Ned M. Smith, Beaverton, OR (US);

Sachin Agrawal, Hillsboro, OR (US);

Sebastian Salomon, North Plains, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 17/00 (2019.01); G06F 13/00 (2006.01); G06F 12/14 (2006.01); G06F 12/00 (2006.01); G06F 7/04 (2006.01); G06F 21/62 (2013.01); G06F 13/10 (2006.01); G06F 21/57 (2013.01); G06F 21/55 (2013.01); G06F 21/82 (2013.01);
U.S. Cl.
CPC ...
G06F 21/6218 (2013.01); G06F 13/102 (2013.01); G06F 21/554 (2013.01); G06F 21/575 (2013.01); G06F 21/82 (2013.01);
Abstract

Systems and techniques for trustworthy peripheral transfer of ownership are described herein. A unique peripheral identifier may be received from an ownership manifest of the peripheral device. The unique peripheral identifier may be transferred to a bus controller for a bus between the computing device and the peripheral device. A measurement may be received from the peripheral device by the basic input and output system of the computing device. A measurement of a computing platform of the computing device may be generated. The measurement may indicate peripheral devices interconnected to the computing device. Data transfer between the peripheral device and the computing device may be allowed via the bus based on validation of the measurement of the computing platform against a platform configuration register of the computing device.


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