The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Oct. 15, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Arif A. Siddiqi, Milpitas, CA (US);

Juhan Kim, Santa Clara, CA (US);

Mahbub Rashed, Cupertino, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 3/20 (2006.01);
U.S. Cl.
CPC ...
G05F 3/205 (2013.01); G11C 5/146 (2013.01);
Abstract

Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal.


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