The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Jan. 16, 2019
Applicant:

Elenion Technologies, Llc, New York, NY (US);

Inventors:

David Henry Kinghorn, Carpinteria, CA (US);

Ari Jason Novack, New York, NY (US);

Holger N. Klein, Santa Barbara, CA (US);

Nathan A. Nuttall, Castaic, CA (US);

Kishor V. Desai, Fremont, CA (US);

Daniel J. Blumenthal, Santa Barbara, CA (US);

Michael J. Hochberg, New York, NY (US);

Ruizhi Shi, New York, NY (US);

Assignee:

Elenion Technologies, LLC, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); G02B 6/13 (2006.01); G02B 6/136 (2006.01); H01L 25/00 (2006.01); G02B 6/12 (2006.01); H01L 25/16 (2006.01); H01L 31/12 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
G02B 6/423 (2013.01); G02B 6/131 (2013.01); G02B 6/136 (2013.01); G02B 6/4238 (2013.01); G02B 6/4251 (2013.01); G02B 6/4268 (2013.01); G02B 6/4274 (2013.01); H01L 25/16 (2013.01); H01L 25/162 (2013.01); H01L 25/50 (2013.01); H01L 31/125 (2013.01); H01L 31/18 (2013.01); G02B 6/4232 (2013.01); G02B 2006/121 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12097 (2013.01); H01L 25/167 (2013.01);
Abstract

Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.


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