The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Nov. 28, 2018
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventor:

Francois Pelletier, Quebec, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/14 (2006.01); G02B 6/122 (2006.01); G02B 6/126 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
G02B 6/14 (2013.01); G02B 6/122 (2013.01); G02B 6/126 (2013.01); G02B 2006/12152 (2013.01);
Abstract

Systems and methods for non-hermetic Semiconductor Optical Amplifier (SOA) integration on a Silicon photonic (SiP) chip using Complementary Metal-Oxide-Semiconductor (CMOS) processes include creating a trench for placement of the SOA, wherein the trench is between two Spot Size Converters (SSCs) located on the SiP chip outside of the trench; forming pedestals in the trench in one or more existing CMOS layers of the SiP chip to guide vertical alignment of the SOA with the SSCs during its placement; and depositing metallic traces and a solder pattern in the trench above the pedestals to enable the SOAs to electrically bond and rest on the pedestals during reflow.


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