The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Mar. 14, 2017
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Materials Co., Ltd., Yokohama-Shi, Kanagawa, JP;

Inventors:

Hiroyasu Kondo, Kanagawa, JP;

Tomoyuki Oozeki, Kanagawa, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 3/38 (2006.01); H01L 23/498 (2006.01); H01L 23/15 (2006.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0306 (2013.01); H01L 23/13 (2013.01); H01L 23/15 (2013.01); H01L 23/49827 (2013.01); H05K 1/11 (2013.01); H05K 1/0346 (2013.01); H05K 3/381 (2013.01); H05K 2201/068 (2013.01); H05K 2203/11 (2013.01);
Abstract

The present invention provides a ceramic circuit board comprising: a ceramic substrate; and at least one of a recess and a through-hole formed in the ceramic substrate, wherein a conductive portion filled with a conductor is provided in the recess or the through-hole, the surface roughness Ra is 1.0 μm or less, and the maximum height Rz is 100 μm or less. It is preferable that the maximum height Rz is 10 μm or less. Further, it is preferable that the surface roughness Ra is 0.5 μm or less. According to the above-described configuration, it is possible to provide a ceramic circuit board having an excellent positionability of the conductive portion for mounting a semiconductor element.


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