The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 24, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chia-Hsiang Chen, Santa Clara, CA (US);

Wei Tang, Hillsboro, OR (US);

Farhana Sheikh, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01); H04L 1/18 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1122 (2013.01); H03M 13/114 (2013.01); H03M 13/116 (2013.01); H03M 13/1134 (2013.01); H03M 13/1137 (2013.01); H04L 1/18 (2013.01);
Abstract

A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.


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