The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

May. 15, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Chung Chen, Keelung, TW;

Chi-Feng Huang, Hsinchu County, TW;

Victor Chiang Liang, Hsinchu, TW;

Chung-Hao Chu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 31/032 (2006.01); H01L 29/94 (2006.01); H01L 29/10 (2006.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/76816 (2013.01); H01L 23/5283 (2013.01);
Abstract

Provided is a semiconductor device including a substrate having a first conductivity type, an isolation structure, a well region having the first conductivity type, a gate structure, and doped regions having a second conductivity type. The isolation structure is disposed in the substrate to form an active region of the substrate. The well region is disposed in the active region and surrounds sidewalls of the isolation structure to form a native region in the active region. The gate structure is disposed over the substrate in the native region. The doped regions are disposed respectively in the well region and the native region of the substrate at two sides of the gate structure. A method of fabricating the semiconductor device is also provided.


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