The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Aug. 30, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yuya Maeda, Atsugi Kanagawa, JP;

Hidenori Miyagawa, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.


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