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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10672769 B1

PDFFull Text
Date of Patent:
Jun. 02, 2020

Filed:

May. 25, 2018

Method of fabricating a transistor having a drain pad with capping and silicide layers

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Hao Chang, Hsinchu, TW;

Ming-Shan Shieh, Hsinchu, TW;

Cheng-Long Chen, Hsinchu, TW;

Wai-Yi Lien, Hsinchu, TW;

Chih-Hao Wang, Hsinchu County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Maschoff Brennan

Primary Examiner:

Allen L Parker

Assistant Examiner:

Charles N Ausar-El

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 21/285 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823885 (2013.01); H01L 23/485 (2013.01); H01L 29/0676 (2013.01); H01L 29/41741 (2013.01); H01L 29/42356 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H01L 21/76834 (2013.01); H01L 21/76885 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.

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Quick Actions:

Chang, Chia-Hao. (2020). Method of fabricating a transistor having a drain pad with capping and silicide layers (U.S. Patent No. 10672769). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10672769

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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