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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10672479 B1

PDFFull Text
Date of Patent:
Jun. 02, 2020

Filed:

Sep. 11, 2018

Nonvolatile memory devices, memory systems and methods of operating nonvolatile memory devices for processing user data

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Taek-Soo Kim, Suwon-si, KR;

Chan-Ik Park, Seongnam-si, KR;

Hyun-Sung Shin, Seoul, KR;

Sang-Hoan Chang, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Tha-O H Bui

Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 19/28 (2006.01); G11C 29/42 (2006.01); G11C 8/14 (2006.01); G11C 7/18 (2006.01); H01L 27/11526 (2017.01); G11C 5/14 (2006.01); G11C 14/00 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); G11C 29/04 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 7/1006 (2013.01); G11C 7/1057 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 19/287 (2013.01); G11C 29/42 (2013.01); G11C 5/147 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 14/0054 (2013.01); G11C 16/0483 (2013.01); G11C 2029/0411 (2013.01); H01L 27/1157 (2013.01); H01L 27/11526 (2013.01); H01L 27/11582 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

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