The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Feb. 20, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jiaxiang Shi, Singapore, SG;

Vinay Sharma, Singapore, SG;

Ingo Volkening, Singapore, SG;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/16 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01);
Abstract

Systems, methods, and circuitries adapt a system-on-chip (SoC) for use with different external devices. In one example, an SOC includes a plurality of SoC data lanes configured to conduct data signals between the SoC and an external device interface. The SoC also includes an interface lane adaptor and a device interface including a plurality of interface connectors. The interface lane adaptor circuitry includes a plurality of SoC adaptor connectors connected to the interface connectors; a plurality of external adaptor connectors connected to the SoC data lanes and configured to be connected to the external device interface; a lane selector circuitry configured to connect a selected one of a first or a second SoC adaptor connector to a selected SoC data lane; and a lane configuration circuitry configured to control the lane selector circuitry to connect either the first or the second SoC adaptor connector to the selected SoC data lane.


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