The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Dec. 21, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andres Malavasi Mora, Hillsboro, OR (US);

Jaydeep Kulkarni, Portland, OR (US);

Anupama Thaploo, Folsom, CA (US);

Muhammad Khellah, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/082 (2006.01); H03K 19/0175 (2006.01); H03K 19/0948 (2006.01);
U.S. Cl.
CPC ...
H03K 19/082 (2013.01); H03K 19/017509 (2013.01); H03K 19/0948 (2013.01);
Abstract

Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.


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