The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Oct. 05, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventor:

Jeffrey Earl, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/13 (2014.01); H03K 5/133 (2014.01); H03K 5/06 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/133 (2013.01); H03K 5/06 (2013.01); H03K 2005/00019 (2013.01);
Abstract

A delay line can include a number of delay elements connected in series, each selected to impart an overall delay to an input signal. The delay line can include delay selection logic to select a subset of the delay elements to delay the input signal. The delay line can include delay element enable logic to enable the selected subset of the delay elements to delay the input signal. Further, the remaining delay elements can be disabled from contributing any delay to the input signal, and a respective periodic signal can be provided to at least one of the remaining delay elements to cause the at least one remaining delay elements to output an output signal that is a function of the respective periodic signal and that has a frequency less than that of the input signal. This configuration can reduce asymmetric aging effects on the delay line.


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