The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jul. 13, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Wen-Shun Lo, Hsinchu County, TW;

Felix Ying-Kit Tsui, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/872 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 29/0607 (2013.01); H01L 29/08 (2013.01); H01L 29/66143 (2013.01); H01L 27/0629 (2013.01); H01L 29/7833 (2013.01);
Abstract

Present disclosure provides a semiconductor structure, including a semiconductor substrate having a top surface, a first well region of a first conductivity type in the semiconductor substrate, a second well region of a second conductivity type in the semiconductor substrate, laterally surrounding the first well region, and an isolation region in the first well region and the second well region in proximity to the top surface. The first well region includes a first lighter doped region in proximity to the top surface, and a heavier doped region under the first lighter doped region. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.


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