The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jun. 05, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jeffrey A. Kessenich, Vancouver, WA (US);

Joemar Sinipete, Boise, ID (US);

Chiming Chu, Boise, ID (US);

Jason L. Nevill, Boise, ID (US);

Kenneth W. Marr, Boise, ID (US);

Renato C. Padilla, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/34 (2006.01); G11C 29/04 (2006.01); G01R 31/02 (2006.01); G11C 16/10 (2006.01); G11C 29/02 (2006.01); G11C 8/08 (2006.01); G11C 7/00 (2006.01); G11C 29/50 (2006.01); G11C 7/02 (2006.01); G01R 31/28 (2006.01); G01R 31/30 (2006.01); G11C 16/26 (2006.01); G11C 29/12 (2006.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G01R 31/02 (2013.01); G01R 31/2853 (2013.01); G01R 31/2856 (2013.01); G01R 31/3008 (2013.01); G11C 7/00 (2013.01); G11C 7/02 (2013.01); G11C 8/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/02 (2013.01); G11C 29/025 (2013.01); G11C 29/04 (2013.01); G11C 29/50008 (2013.01); G01R 31/025 (2013.01); G11C 16/00 (2013.01); G11C 16/349 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5006 (2013.01);
Abstract

Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.


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