Pseudo static random access memory and control method thereof

Abstract

In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.