The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Dec. 01, 2016
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

G. Glenn Henry, Austin, TX (US);

Douglas R. Reed, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/08 (2006.01); G06N 3/08 (2006.01); G06F 12/0846 (2016.01); G06F 12/0813 (2016.01); G06F 12/0897 (2016.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 12/08 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0846 (2013.01); G06F 12/0897 (2013.01); G06N 3/04 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/2515 (2013.01);
Abstract

A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.


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