The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

May. 08, 2017
Applicant:

Ihp Gmbh—innovations for High Performance Microelectronics/leibniz-institut Fur Innovative, Frankfurt (Oder), DE;

Inventor:

Roland Sorge, Frankfurt, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 21/823493 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/0696 (2013.01); H01L 29/41758 (2013.01); H01L 29/78 (2013.01); H01L 21/823481 (2013.01); H01L 21/823892 (2013.01); H01L 29/0878 (2013.01); H01L 29/66712 (2013.01); H01L 29/7803 (2013.01);
Abstract

A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well region, comprising doped source and drain regions of a second conductivity type and at least one MOS channel region extending between the source and drain regions under a respective gate stack, and a dielectric isolation layer of the STI or LOCOS type and laterally surrounding same, wherein well portions of the well region adjoin the MOS channel region in the two opposite longitudinal directions oriented perpendicular to a notional connecting line extending from the source through the MOS channel region to the drain region, and which extend as far as a surface of the active MOS transistor region, so that the respective well portion adjoining the MOS channel region is arranged between the MOS channel region and the dielectric isolation layer.


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