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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10658391 B1

PDFFull Text
Date of Patent:
May. 19, 2020

Filed:

Dec. 16, 2016

Hybrid substrate engineering in cmos finfet integration for mobility improvement

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chia-Yu Chen, White Plains, NY (US);

Bruce B. Doris, Slingerlands, NY (US);

Hong He, Schenectady, NY (US);

Rajasekhar Venigalla, Hopewell Junction, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Vazken Alexanian

Primary Examiner:

Didarul A Mazumder

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/30 (2006.01); H01L 21/82 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02532 (2013.01); H01L 21/308 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/1207 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/7842 (2013.01); H01L 29/7848 (2013.01); H01L 21/823864 (2013.01);
Abstract

A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

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