The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Jun. 30, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 23/48 (2006.01); H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 23/532 (2006.01); G11C 8/14 (2006.01); H01L 21/3205 (2006.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5329 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 21/32053 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 27/24 (2013.01); H01L 27/2481 (2013.01);
Abstract
A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.