The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Sep. 10, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tomoya Kawai, Kawasaki, JP;

Takashi Ishida, Yokkaichi, JP;

Shuichi Toriyama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); H01L 27/1157 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53209 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); H01L 23/528 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 27/11573 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.


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