The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Mar. 04, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Shoichi Iriguchi, Beppu, JP;

Hiroyuki Sada, Beppu, JP;

Genki Yano, Beppu, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); B23K 26/364 (2014.01); B23K 101/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); B23K 26/364 (2015.10); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/6836 (2013.01); H01L 24/09 (2013.01); H01L 24/49 (2013.01); H01L 24/97 (2013.01); B23K 2101/40 (2018.08);
Abstract

In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.


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