The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Dec. 23, 2016
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Stmicroelectronics SA, Montrouge, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Nicolas Posseme, Sassenage, FR;

Maxime Garcia-Barros, Ivry sur Seine, FR;

Yves Morand, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/324 (2006.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 21/223 (2006.01); H01L 21/322 (2006.01); H01L 21/447 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/324 (2013.01); H01L 21/02057 (2013.01); H01L 21/2236 (2013.01); H01L 21/31155 (2013.01); H01L 21/3221 (2013.01); H01L 21/447 (2013.01); H01L 21/762 (2013.01); H01L 29/4908 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66507 (2013.01); H01L 29/66545 (2013.01); H01L 29/66628 (2013.01); H01L 29/66772 (2013.01); H01L 29/7827 (2013.01); H01L 21/223 (2013.01); H01L 21/823468 (2013.01);
Abstract

There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.


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