The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Mar. 13, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Kazutaka Takizawa, Yokohama Kanagawa, JP;

Yoshihisa Kojima, Kawasaki Kanagawa, JP;

Masaaki Niijima, Machida Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 16/3454 (2013.01); G11C 16/0483 (2013.01);
Abstract

According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.


Find Patent Forward Citations

Takizawa, Kazutaka. (2020). Memory system and method for controlling memory system (U.S. Patent No. 10658055). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10658055

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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