The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Dec. 14, 2017
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Kuen-Long Chang, Taipei, TW;

Ken-Hui Chen, Hsin Chu, TW;

Su-Chueh Lo, Hsinchu, TW;

Chun-Yu Liao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 7/06 (2006.01); G06F 12/02 (2006.01); G11C 11/4093 (2006.01); G06F 13/40 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 12/0246 (2013.01); G06F 13/4004 (2013.01); G11C 7/06 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); G11C 11/4093 (2013.01); G11C 16/0483 (2013.01); G11C 16/20 (2013.01);
Abstract

The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.


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