The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Mar. 03, 2015
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
Jongtae Kwak, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03L 7/081 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03L 7/181 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/106 (2013.01); G11C 7/1051 (2013.01); G11C 7/1066 (2013.01); G11C 7/22 (2013.01); H03K 3/012 (2013.01); H03K 3/0375 (2013.01); H03L 7/0814 (2013.01); H03L 7/181 (2013.01);
Abstract
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.