The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jun. 15, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Marcos Mauricio Pelicia, Campinas, BR;

Alex Rocha Prado, Campinas, BR;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01); G05F 1/613 (2006.01); G05F 1/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/613 (2013.01); G05F 1/00 (2013.01); G05F 1/56 (2013.01);
Abstract

A power management system is provided. The power management system includes a first voltage regulator having an input coupled to a first voltage supply terminal and an output. The first voltage regulator is configured to provide an operating voltage at the output. A second voltage regulator has an input coupled to the output of the first voltage regulator. The second voltage regulator is configured to provide at an output a retention voltage based on a control signal. A control circuit is coupled to the second voltage regulator and configured to provide the control signal to the second voltage regulator.


Find Patent Forward Citations

Pelicia, Marcos. (2020). Power management for logic state retention (U.S. Patent No. 10656665). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10656665

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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