The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Feb. 01, 2018
Oracle International Corporation, Redwood City, CA (US);
Mark Semmelmeyer, Sunnyvale, CA (US);
Ali Vahidsafa, Santa Clara, CA (US);
Sebastian Turullols, Santa Clara, CA (US);
Scott Cooke, Townsend, MA (US);
Senthilkumar Diraviam, Sunnyvale, CA (US);
Preethi Sama, Santa Clara, CA (US);
ORACLE INTERNATIONAL CORPORATION, Redwood, CA (US);
Abstract
Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.