The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Sep. 21, 2018
Applicant:

Pdf Solutions, Inc., Santa Clara, CA (US);

Inventors:

Brian Stine, San Jose, CA (US);

Richard Burch, San Jose, CA (US);

Nobuchika Akiya, San Jose, CA (US);

Assignee:

PDF Solutions, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01); G01R 31/3177 (2006.01); G06N 20/00 (2019.01); G01R 31/317 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01); G06N 20/10 (2019.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31717 (2013.01); G06N 3/0454 (2013.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01);
Abstract

Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having 'good' circuit traces are subjected to thermal stress for less time than for chips identified as having 'bad' circuit traces.


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