The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 03, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Siva P. Adusumilli, South Burlington, VT (US);

John J. Ellis-Monaghan, Grand Isle, VT (US);

Anthony K. Stamper, Williston, VT (US);

Ian McCallum-Cook, Burlington, VT (US);

Mark Goldstein, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/32 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/265 (2006.01); C23C 16/48 (2006.01); H01L 21/762 (2006.01); C23C 16/40 (2006.01); H01L 29/04 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/32 (2013.01); C23C 16/402 (2013.01); C23C 16/481 (2013.01); H01L 21/266 (2013.01); H01L 21/26533 (2013.01); H01L 21/26586 (2013.01); H01L 21/76243 (2013.01); H01L 21/76267 (2013.01); H01L 21/76289 (2013.01); H01L 29/04 (2013.01); H01L 29/66772 (2013.01); H01L 29/78603 (2013.01);
Abstract

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.


Find Patent Forward Citations

Adusumilli, Siva. (2020). Substrates with self-aligned buried dielectric and polycrystalline layers (U.S. Patent No. 10651281). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10651281

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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