The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Sep. 05, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

David Pritchard, Glenville, NY (US);

Lixia Lei, Clifton Park, NY (US);

Francisco Ledesma Rabadan, Richardson, TX (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 23/60 (2006.01); H01L 21/66 (2006.01); G01R 31/28 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); G01R 31/2812 (2013.01); H01L 22/32 (2013.01); H01L 22/34 (2013.01); H01L 23/5256 (2013.01); H01L 22/14 (2013.01);
Abstract

When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.


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