logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10651134 B1

PDFFull Text
Date of Patent:
May. 12, 2020

Filed:

Mar. 01, 2019

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey Gelorme, Burlington, CT (US);

Li-Wen Hung, Mahopac, NY (US);

John U. Knickerbocker, Monroe, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Fleit Intellectual Property Law

Donna Flores

Primary Examiner:

William F Kraig

Assistant Examiner:

Vicki B Booker

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/76898 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/83855 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A method of manufacturing a multi-layer wafer is provided. At least one stress compensating polymer layer is applied to at least one of two heterogeneous wafers. The stress compensating polymer layer is low temperature bonded to the other of the two heterogeneous wafers to form a multi-layer wafer pair. Channels are created between die on at least one of the two heterogeneous wafers. The channels are back filled with one of oxide or polymer to create a channel oxide deposition.

Find Patent Forward Citations

Quick Actions:

Gelorme, Jeffrey. (2020). Wafer level integration including design/co-design, structure process, equipment stress management and thermal management (U.S. Patent No. 10651134). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10651134

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…