The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Aug. 09, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

John Edward Barth, Jr., Williston, VT (US);

Kevin W. Gorman, Essex, VT (US);

Harold Pilo, Underhill, VT (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01); G11C 29/14 (2006.01); G11C 29/36 (2006.01); G11C 7/18 (2006.01); G11C 29/12 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 29/14 (2013.01); G11C 7/18 (2013.01); G11C 11/419 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/36 (2013.01);
Abstract

A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.


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