The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 20, 2018
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventor:

Koichi Iwao, Kodaira, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/10 (2006.01); G01R 31/317 (2006.01); G06K 9/00 (2006.01); B60R 11/04 (2006.01); G06T 1/60 (2006.01); G01R 31/3187 (2006.01); G11C 29/26 (2006.01); G11C 29/16 (2006.01); G11C 29/38 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); B60R 11/04 (2013.01); G01R 31/3187 (2013.01); G01R 31/31703 (2013.01); G01R 31/31724 (2013.01); G06K 9/00805 (2013.01); G06T 1/60 (2013.01); G11C 29/10 (2013.01); G11C 29/16 (2013.01); G11C 29/26 (2013.01); G11C 29/38 (2013.01); G11C 2029/5602 (2013.01); G11C 2029/5604 (2013.01);
Abstract

An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.


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