The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2020
Filed:
Sep. 13, 2018
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H01L 29/786 (2006.01); H01L 29/24 (2006.01); H01L 29/04 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 27/1218 (2013.01); H01L 27/1225 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/24 (2013.01); H01L 29/4908 (2013.01); H01L 29/4916 (2013.01); H01L 29/517 (2013.01); H01L 29/66969 (2013.01); H01L 29/78603 (2013.01);
Abstract
The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.