The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Apr. 12, 2018
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Wei Lee, New Taipei, TW;

Cheng-Hsien Cheng, Yunlin, TW;

Shaw-Hung Ku, Taipei, TW;

Atsuhiro Suzuki, Hsincu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 27/11582 (2013.01);
Abstract

A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.


Find Patent Forward Citations

Loading…