The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2020
Filed:
Aug. 15, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Meng-Han Lin, Hsinchu, TW;
Chih-Ren Hsieh, Changhua, TW;
Wei Cheng Wu, Zhubei, TW;
Chih-Pin Huang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is formed on the memory region and a dummy structure is formed on the isolation structure. A boundary sidewall spacer is formed covering the dummy structure. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.