The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Aug. 22, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Zheng Hao Gan, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/112 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 23/525 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 21/823431 (2013.01); H01L 23/5256 (2013.01); H01L 27/0886 (2013.01); H01L 29/7851 (2013.01);
Abstract

Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one FinFET device. The FinFET device includes a substrate, a plurality of fins protruding from the substrate, at least one gate structure on the substrate and across the plurality of fins by covering portions of side and top surfaces of the plurality of fins, and source/drain regions formed in the plurality of fins at two sides of the gate structure. The semiconductor device also includes a Fuse device formed above the FinFET device. The Fuse device includes a positive terminal and a negative terminal. The negative terminal is electrically connected to at least one source region of the FinFET device and the positive terminal is electrically connected to an external pad. Further, the semiconductor device also includes a dielectric layer formed between the FinFET device and the Fuse device.


Find Patent Forward Citations

Gan, Zheng. (2020). Semiconductor device and fabrication method thereof (U.S. Patent No. 10644010). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10644010

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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