The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Jun. 20, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Feng Ping Cai, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/94 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/04941 (2013.01);
Abstract

A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed.


Find Patent Forward Citations

Loading…