The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Sep. 07, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Qanit Takmeel, Latham, NY (US);

Somnath Ghosh, Clifton Park, NY (US);

Anbu Selvam K M Mahalingam, Mechanicville, NY (US);

Craig M. Child, Gansevoort, NY (US);

Sunil K. Singh, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/02167 (2013.01); H01L 21/2885 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76819 (2013.01); H01L 21/76846 (2013.01); H01L 21/76847 (2013.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to via structures and via patterning using oblique angle deposition processes. The method includes: depositing a material on a lower wiring layer; forming one or more openings in the material; filling the one or more openings with a conductive material; growing via structures on the conductive material; forming interlevel dielectric material on the via structures; and forming an upper wiring layer on the interlevel dielectric material and in contact with the via structures.


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