The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Dec. 19, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Violante Moschiano, Avezzano, IT;

Raffaele Bufano, Tremestieri Etneo, IT;

Mirko Scapin, San Giorgio delle Pertiche, IT;

Andrea Giovanni-Xotta, Cornedo Vicentino, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 8/12 (2006.01); G11C 16/04 (2006.01); G11C 11/408 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 8/12 (2013.01); G11C 11/4085 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/3427 (2013.01);
Abstract

A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.


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