The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Sep. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Himanshu Kaul, Portland, OR (US);

Mark Anders, Hillsboro, OR (US);

Seongjong Kim, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 17/15 (2006.01); G06F 9/38 (2018.01); H03K 19/21 (2006.01); G06N 3/063 (2006.01); G06F 7/544 (2006.01); G06N 3/04 (2006.01); G06F 30/39 (2020.01); G06F 7/501 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/3885 (2013.01); G06F 15/8053 (2013.01); G06F 17/15 (2013.01); G06F 17/16 (2013.01); G06F 30/39 (2020.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); H03K 19/21 (2013.01); G06F 7/501 (2013.01); G06F 2207/382 (2013.01);
Abstract

A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An embodiment includes M slices, each of which calculates the vector dot products between a corresponding segment of the first and the second N-bit vectors. Each of the slices outputs intermediary multiplier results for the lower precision modes, but not for highest precision mode. A plurality of adder trees to sum up the plurality of intermediate multiplier results, with each adder tree producing a respective adder out result. An accumulator to merge the adder out result from a first adder tree with the adder out result from a second adder tree to produce the vector dot product of the first and the second N-bit vector in the highest precision mode.


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