The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 08, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Makoto Senoo, Kanagawa, JP;

Katsutoshi Suito, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G01R 31/3183 (2006.01); G06T 7/00 (2017.01); G11C 29/44 (2006.01); G01R 31/303 (2006.01); G11C 16/26 (2006.01); G11C 29/12 (2006.01); G11C 16/16 (2006.01); G11C 8/08 (2006.01); G11C 29/02 (2006.01); G11C 16/22 (2006.01); G11C 29/56 (2006.01); G11C 29/04 (2006.01); G11C 29/50 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31835 (2013.01); G01R 31/303 (2013.01); G06T 7/0006 (2013.01); G11C 8/08 (2013.01); G11C 16/16 (2013.01); G11C 16/225 (2013.01); G11C 16/26 (2013.01); G11C 29/025 (2013.01); G11C 29/12005 (2013.01); G11C 29/44 (2013.01); G11C 29/56 (2013.01); G06T 7/001 (2013.01); G06T 2207/30148 (2013.01); G11C 16/20 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5006 (2013.01);
Abstract

A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.


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