The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jun. 01, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shang-Fu Yeh, Hsinchu, TW;

Kuo-Yu Chou, Hsinchu, TW;

Calvin Yi-Ping Chao, Hsinchu County, TW;

Chih-Lin Lee, Miaoli County, TW;

Chin Yin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/374 (2011.01); H04N 5/376 (2011.01); H03M 1/00 (2006.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3765 (2013.01); H03M 1/007 (2013.01); H04N 5/378 (2013.01); H04N 5/3745 (2013.01);
Abstract

A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.


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