The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Dec. 08, 2017
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Sanjay Dandia, San Jose, CA (US);

Gerald R. Talbot, Concord, MA (US);

Mahesh S. Hardikar, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/89 (2013.01);
Abstract

An integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate. The conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion. The isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion. The isolated conductor portion may surround a portion of a perimeter of the conductor portion. The isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.


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