The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Apr. 24, 2019
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Inventors:

Shoji Watanabe, Nagano, JP;

Ken Miyairi, Nagano, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/13 (2013.01); H01L 23/145 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A wiring substrate includes a stack having a plurality of insulation layers and a plurality of wiring layers. Each of the plurality of insulation layer is formed by an insulative resin of which main component is a photosensitive resin. The plurality of insulation layers and the plurality of wiring layers are alternately stacked one upon another. The wiring substrate further includes a first insulation layer covering a lower surface of the stack and entirely covering a side surface of the stack. The first insulation layer has a higher rigidity than the plurality of insulation layers. An upper surface of the uppermost one of the plurality of wiring layers and an upper surface of the uppermost one of the plurality of insulation layers are exposed from the first insulation layer.


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